Member of Technical Staff - Physical Design
Architect Labs · Palo Alto
About Architect Labs
Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, OEMs and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.
What You'll Do
As our first Physical Design engineer, you'll build the PD function from scratch and extend our AI system from spec-to-netlist to tapeout-ready GDS. You'll own the methodology and hands-on execution for physical implementation at 3nm, 2nm, and future leading-edge nodes.
Build the methodology: Establish and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.
Own implementation: Personally drive block and full-chip floorplanning, power planning, placement, clock tree synthesis, routing, and ECOs to meet demanding PPA targets.
Drive signoff: Define release criteria and close timing, signal integrity, EM/IR, DRC/LVS, and foundry-required physical checks through final GDS delivery.
Work with AI researchers: Translate PD expertise into automated flows, structured tool feedback, and evaluations. Feed post-route results back into architecture, RTL, and our AI system.
Lead technical partnerships: Resolve process, library, tool, and signoff challenges directly with foundries, EDA vendors, and IP providers.
Build the team: Set technical standards, define the PD roadmap and hiring priorities, and mentor future hires while remaining hands-on.
What We'd Like to See
Qualifications & Skills:
Tapeout ownership: Multiple production tapeouts, with direct physical implementation and signoff responsibility at 3nm or 2nm and experience leading full-chip closure.
Methodology development: A track record of building production PD methodology from scratch for advanced nodes, including PDK/library qualification, tool evaluation, and deployment across chip programs.
Technical depth: Deep expertise in hierarchical implementation, multi-mode multi-corner timing analysis, variation, clocking, congestion, low-power design, extraction, and power integrity.
EDA expertise: Recent hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus, along with commercial timing, extraction, power integrity, and physical verification tools.
Automation: Strong Tcl and Python skills, with experience building maintainable flow scripts, automated checks, regressions, and actionable PPA reporting.
Technical leadership: Ability to independently establish the flow, debug difficult closure problems, and explain implementation trade-offs to hardware, software, and AI teams.
Bonus:
Direct 2nm methodology bring-up and tapeout experience, including GAA/nanosheet implementation and evolving PDK or library qualification.
Implementation of high-performance CPUs, GPUs, AI accelerators, or complex custom SoCs with demanding frequency and power targets.
Experience with design-technology co-optimization, chiplets, multi-die integration, or backside power delivery where supported by the target process.
Prior experience as a founding PD engineer or building methodology adopted across multiple teams and chip programs.
What We Offer
Competitive compensation and meaningful equity, autonomy to establish the PD function, and the opportunity to shape AI-driven silicon design from implementation through tapeout.
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