Senior Design Engineer
Cohu · TW
Senior Digital Verification Engineer
Cohu is a global technology and market leader in semiconductor test and inspection metrology markets. Our advanced systems are critical to ensuring the quality and reliability of the next generation of electronics. This role is a key part of the team developing our state-of-the-art 26 GHz RF semiconductor tester platform, leveraging cutting-edge Xilinx Versal ACAP technology to achieve unparalleled performance. Learn more at cohu.com.
Cohu is seeking a Senior Digital Verification Engineer to join our expanding digital team. This critical role focuses on verifying complex digital designs for our power IC, RF, digital, and mixed-signal test solutions within the Versal ACAP. The successful candidate will utilize advanced tools and methodologies—including SystemVerilog (UVM) and Cadence vManager—to develop and execute comprehensive verification plans that ensure first-pass silicon success for our high-performance hardware.
Key Responsibilities
- Verification Strategy and Planning
- Develop and implement detailed, reusable test plans and verification strategies based on design requirements, architecture specifications, and product functional objectives.
- Environment Development
- Create and maintain robust, scalable verification environments using SystemVerilog and the Universal Verification Methodology (UVM).
- Test Development and Execution
- Write, execute, and manage targeted and constrained-random tests to verify functionality at various abstraction levels (unit, block, and full system).
- Verification IP and Modeling
- Develop reusable Verification IP (vIP) and Bus Functional Models (BFMs) to accurately simulate and verify interfaces (e.g., AMBA/AXI, I²C, SPI).
- Model-Based Verification
- Implement verification testbenches and comparison points derived from MathWorks Simulink models to ensure algorithms implemented in RTL match golden reference models.
- Coverage and Debugging
- Analyze test results, identify coverage gaps, and perform root-cause debugging of design issues in collaboration with the RTL design team.
- Utilize platforms such as Cadence vManager for regression management and coverage closure.
- Automation and Infrastructure
- Develop scripts (e.g., Python) for results processing, automated regression control, and streamlined CI/CD flows.
- Documentation and Review
- Provide timely progress reports, escalate critical issues when necessary, and actively participate in formal design and verification reviews.
Qualifications and Experience
- Required Background
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Strong problem-solving, analytical, and communication skills (both written and verbal).
- GPA of 3.0 or higher.
- Proficiency in at least one scripting language (e.g., Python, Perl) for automation and data processing.
- Extensive experience working in a UNIX/Linux development environment.
- Technical Expertise (Must Have)
- Expertise in hardware verification languages: SystemVerilog and UVM.
- Experience with advanced verification tools, particularly Cadence vManager (or similar regression management frameworks).
- Strong foundation in C/C++ for model creation and co-simulation.
- Experience with SoC verification.
- Understanding of DSP verification methodologies.
- Highly Desired Skills and Domain Knowledge
- Familiarity with Model-Based Design tools such as MathWorks Simulink for developing test vectors and reference models.
- Working knowledge of embedded SoC fabric and ARM architecture (e.g., Cortex-A series).
- Experience with hardware/software co-verification techniques and validating register maps accessed by firmware.
- Practical experience with the overall FPGA/ASIC development and implementation flow.
- Familiarity with high-speed protocols and the challenges of verifying designs used for RF/mixed-signal applications.