Senior Engineer (Level 2)

eInfochips · Hyderabad

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Position:

Job Description:

Principal Accountabilities

• Responsible for  floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR Flow
• Execute the block level place and route assignments from Netlist through GDS flow
• Perform full chip implementation of complex SoCs (RTL-to-GDSII)  if needed.
• Close STA timing across all corners and modes for blocks and should be able to generate ECO independently .
• Work with design teams for closing CTS, IO timing, DFT timing.
• Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
• Ensure successful delivery of blocks to customers

Job Complexity

• Requires in-depth knowledge and experience
• Solves complex problems; takes a new perspective using existing solutions
• Works independently; receives minimal guidance
• Acts as a resource for colleagues with less experience
• Represents the level at which career may stabilize for many years or even until retirement
• Contributes to process improvements
• Typically resolves problems using existing solutions
• Provides informal guidance to junior staff
• Works with minimal guidance

Experience / Education
Typically requires 5–7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.

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