Senior Design Verification Engineer
onsemi · Brno
Join onsemi’s new and growing RISC-V division and help ensure the functional correctness, quality, safety, and security of configurable and customizable RISC-V CPU IP.
You will participate in the complete verification process, from understanding requirements and defining verification plans and strategies to implementation, debugging, metric-driven verification closure, tape-out, and delivery of reviewable evidence.
You will combine proven SystemVerilog/UVM simulation methodologies with innovative and advanced formal verification techniques. You will also help define practical AI-assisted verification approaches focused on measurable quality and engineering effectiveness, not simply producing unchecked AI-generated content.
More details about our company benefits can be found here: