Principal Physical Design Engineer

Celero Communications · San Jose · $150,000–$250,000 (stated in the posting)

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Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry’s first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet’s CapitalG has backed Celero at a $3B valuation. As we continue to grow, we’re hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.

We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

Core Responsibilities

• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness. 

Key Qualifications

• Must have 7+ years of relevant ASIC physical design experience (depending on degree level).
• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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