APAC Algo Trading Low Latency C++ Developer
UBS · China
Join a high-performance team building ultra-low latency trading systems where nanoseconds matter. You’ll design and implement a trading rules engine for real-time controls using a hybrid of FPGA hardware and high-performance C++, enabling deterministic execution and rapid interaction with the markets.• Design and implement real-time trading rules and risk checks using FPGA (Verilog/VHDL) or C++.
• Architect cycle-accurate FPGA designs and high-speed network interfaces (10/25/40/100GbE, RoCEv2) is preferred.
• Build simulation and verification frameworks for FPGA reliability.
• Drive full FPGA design flow (synthesis, place & route, timing closure).
• Interface C++ applications with FPGA hardware for real-time orchestration.
• Implement lock-free data structures and concurrency control in Linux.
• Build low-latency network apps using kernel bypass (e.g., Rivermax).
• Analyze system performance and resolve latency bottlenecks.
• Collaborate with global IT, Quants, and Traders across asset classes.
• Provide Level 3 support for production systems.
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