Staff / Senior Staff Engineer Chip Verification
Infineon · Singapore
We are seeking an experienced Chip Verification Engineer to execute end-to-end verification of complex System-on-Chip designs, with a focus on Network-on-Chip (NoC), interconnect and system-level verification. The role involves developing verification plans, building and integrating SystemVerilog/UVM testbenches and VIPs, creating C/C++ and Perspec test cases, and performing simulation and debugging across RTL, unit-delay and gate-level environments.
Your role
Key responsibilities in your new role
- Execute System-on-Chip (SoC) verification tasks including Network on Chip (NOC) interconnect verification and work closely with team members to review and understand the relevant functional and safety-related requirements.
- Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.
- Execute the verification plan by developing C/C++ and Perspec test cases.
- Develop System Verilog/UVM test bench components and by integrating 3rd party VIP components.
- Simulate and debug at RTL, Unit Delay, and Gate Level using appropriate tools and flows including Emulator, Portable Stimulus, or Formal methodologies for functional and toggle coverage closure.
- For a more senior role, you will also lead a team technically through exploring new environments and identifying potential enhancement areas through new methodology. Identify and set mid/long term goals based on benchmarking against industry standards.
Your profile
Qualifications and skills to help you succeed
- Masters/Bachelors in Electrical Engineering or Computer Science with 5-12 years of relevant work experience.
- Strong foundational knowledge of digital/mixed-signal design &verification.
- Understanding of UPF context of analog/transistor level.
- Advanced knowledge and hands-on experience of System Verilog and UVM Test Bench bring up.
- Understand the usage of tools like Xcelium, Spectre(X) and Simvision.
- Hands-on experience in hardware-software debugging at the system or application level.
- Hand-on experience with gate-level-simulations and with debugging/troubleshooting skills.
- Exposure to version-controlling (eg, Gitlab, Git/Bitbucket, ClearCase, CVS, SVN) and bug-management schemes.
- Hands on experience in Network on Chip (NOC) verification and AMBA/AHB/AXI with regards to protocol/uVC/VIP integration is a plus.
- Knowledge of Github Copilot, AI/ML and advanced data analytics applied to SoC verification is a strong plus.
- Dynamic and energetic with zero verification escape mindset.
- Self-motivated, flexible, good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners.
- Proven ability to achieve results in a very dynamic, Ulti-site environment and be able to coordinate with priorities and self-initiatives.
- Knowledge on ISO26262 and ISO21434 are advantageous.
- Verification experience in COM, CPU peripherals, BUS protocols or pattern development is a plus. Experience in test bench/verification environment set up is also a plus.
- Candidate who has more relevant working experience will be considered for a more senior position.
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Carol Lee
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