Senior / Staff SoC DRAM System Engineer

Qualcomm · Hsinchu

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GENERAL SUMMARY:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all.

As a Qualcomm DRAM system Engineer, you will design and develop DRAM system software solutions for Qualcomm IE-IOT SoC platforms, spanning Linux and RTOS environments, enabling high-performance, low-power, and real-time DRAM system experiences in heterogeneous edge computing environments. Your work will support a broad range of applications, including surveillance, smart devices, retail systems, robotics, and edge AI in physical world systems, bridging deep technical knowledge with hands-on engineering execution to deliver robust, market-ready products.

Qualcomm DRAM system Engineers collaborate with cross-functional teams to assess and advance the application of company products that meet and exceed customer needs.

PRINCIPAL DUTIES AND RESPONSIBILITIES:

• Design, develop, and evaluate DRAM system solutions for Qualcomm IE-IOT SoC platforms, including DRAM controller, PHY, timing, calibration, and memory subsystem integration across Linux and RTOS environments.
• Lead DRAM bring-up, initialization, tuning, and validation on new SoC and hardware platforms to ensure stable boot, reliable runtime operation, and production readiness.
• Configure and optimize memory controller and PHY settings to meet JEDEC requirements, platform power targets, bandwidth goals, latency constraints, and system-level performance objectives.
• Collaborate with SoC architecture, hardware, PCB, firmware, bootloader, kernel, validation, and DRAM vendor teams to integrate and debug memory subsystem behavior on Qualcomm IE-IOT SoC-based systems.
• Perform DRAM characterization, stress testing, margin analysis, retention testing, and signal/power integrity correlation to identify stability risks and improve operating margins.
• Analyze and resolve system-level memory issues across boot-up, suspend/resume, low-power modes, and runtime workloads, including failures related to timing, calibration, data corruption, bandwidth, and power state transitions.
• Develop and maintain diagnostic tools, automated validation flows, test patterns, and debug procedures to improve DRAM reliability, coverage, and engineering efficiency.
• Conduct detailed design reviews, validation reviews, failure analysis, and technical documentation to ensure DRAM system implementation meets performance, power, reliability, compliance, and cost requirements.
• Prepare and present technical findings, design tradeoffs, validation status, and issue-resolution plans to cross-functional stakeholders and project leadership.
• Participate in defining assignment objectives, planning validation activities, coordinating schedules, and driving DRAM-related deliverables to closure with minimal supervision.

REQUIRED COMPETENCIES:

(All competencies are required upon entry)

• Demonstrates strong knowledge of DRAM subsystem architecture, including LPDDR3/LPDDR4/LPDDR5 operation, DRAM controller behavior, PHY interface, timing parameters, training, and calibration flows.
• Able to lead DRAM bring-up, initialization, configuration, tuning, and validation on new SoC and hardware platforms from early silicon through production readiness.
• Experienced in configuring memory controller and PHY registers to satisfy JEDEC specifications, board-level constraints, power requirements, bandwidth targets, and system-level performance goals.
• Capable of performing DRAM characterization, stress testing, margin sweeps, retention validation, read/write window analysis, and failure reproduction to assess memory stability and operating margins.
• Skilled in analyzing and resolving system-level DRAM issues across boot-up, suspend/resume, low-power modes, and runtime workloads, including timing violations, calibration failures, data corruption, bandwidth bottlenecks, and power-state transition issues.
• Able to collaborate effectively with SoC architecture, PCB, hardware, firmware, bootloader, kernel, validation, and DRAM vendor teams to debug and optimize memory subsystem behavior.
• Experienced in signal integrity and power integrity validation, including working with hardware teams on layout constraints, routing guidelines, SI/PI correlation, and tuning recommendations.
• Able to develop, maintain, and improve automated validation flows, diagnostic tools, memory test patterns, and debug procedures for DRAM reliability, performance, and regression coverage.
• Understands memory bandwidth utilization, latency impact, QoS behavior, and power/performance tradeoffs, and can identify opportunities to improve throughput, reduce power, and enhance system responsiveness.
• Able to document technical findings, validation results, issue analysis, tuning recommendations, and risk assessments clearly for cross-functional stakeholders.
• Occasional business travel across APAC and other regions may be required.

MINIMUM QUALIFICATIONS:

• Master's degree in Electrical Engineering or a related field with 3+ years of relevant experience, or a PhD in a related field.
• Strong understanding of LPDDR3/LPDDR4/LPDDR5 specifications, timing parameters, and calibration schemes.
• Experience in configuring DRAM registers and bring-up on embedded platforms.
• Familiar with memory controller architecture and PHY interface tuning.
• Skilled in using logic analyzers, oscilloscopes, and memory test equipment.
• Comfortable with Linux-based embedded systems and debugging low-level software interactions with DRAM.

PREFERRED QUALIFICATIONS:

• Experience debugging kernel panics or stability issues caused by DRAM misconfiguration.
• Familiarity with memory low-power states, self-refresh, and power-saving strategies.
• Knowledge of post-silicon validation, including test pattern development and validation coverage planning.
• Worked with DRAM vendors to understand datasheets, tuning recommendations, and errata.
• Comfortable working in a globally distributed, cross-disciplinary engineering team.

Minimum Qualifications:

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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If you would like more information about this role, please contact Qualcomm Careers.

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