Sr. Staff Physical Design Engineer
AMD · Vancouver
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Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
Join an experienced physical design team working on AMD graphics IP for next-generation AI data center chips. In this role, you will own and drive complex physical design work for multi-million-gate blocks, delivering designs against challenging performance, power, and area targets using advanced process technologies. You will work closely with RTL design and other engineering partners throughout the project lifecycle, from floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and final signoff. The role also provides opportunities to lead technical execution, establish design methodologies, improve automated design flows, and mentor other engineers.
THE PERSON:
You are a collaborative technical leader who brings strong analytical thinking, clear communication, and attention to detail to complex physical design challenges. You work effectively with RTL and physical design teams to solve problems, navigate technical tradeoffs, and keep designs moving toward closure. You take ownership of execution, communicate issues and priorities clearly across geographically distributed teams, and are comfortable providing technical guidance and mentoring to other engineers. You can balance multiple priorities while keeping the team focused on successful project delivery.
KEY RESPONSIBILITIES:
- Own the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.
- Partner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.
- Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
- Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.
- Establish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.
- Drive design optimization for timing, power, area, and design-cycle efficiency.
- Develop and enhance scripts and automated design flows to improve physical design execution.
- Provide technical leadership and mentoring to engineers throughout design closure.
- Collaborate across geographically distributed engineering teams to deliver projects against technical requirements.
PREFERRED EXPERIENCE:
- Strong experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.
- Experience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.
- Experience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.
- Experience with physical design and signoff tools such as Synopsys ICC2, ICC, Fusion Compiler, PrimeTime and StarRC; Mentor Graphics Calibre; Apache RedHawk; and Cadence Innovus and Genus.
- Experience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.
- Experience with advanced process technologies, including N2P or below.
- Proficiency with Python and TCL for design-flow development and automation.
- Experience leading engineers through design closure and providing technical mentorship.
- Familiarity with RTL design, logic-level optimization, and computer organization/architecture.
- Experience applying or developing AI techniques for performance, power, and area optimization is desirable.
ACADEMIC CREDENTIALS:
- Bachelors or Masters in Electronics/Electrical Engineering preferred.
LOCATIONS:
- Vancouver, BC or Markham, ON
#LI-LC3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
Join an experienced physical design team working on AMD graphics IP for next-generation AI data center chips. In this role, you will own and drive complex physical design work for multi-million-gate blocks, delivering designs against challenging performance, power, and area targets using advanced process technologies. You will work closely with RTL design and other engineering partners throughout the project lifecycle, from floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and final signoff. The role also provides opportunities to lead technical execution, establish design methodologies, improve automated design flows, and mentor other engineers.
THE PERSON:
You are a collaborative technical leader who brings strong analytical thinking, clear communication, and attention to detail to complex physical design challenges. You work effectively with RTL and physical design teams to solve problems, navigate technical tradeoffs, and keep designs moving toward closure. You take ownership of execution, communicate issues and priorities clearly across geographically distributed teams, and are comfortable providing technical guidance and mentoring to other engineers. You can balance multiple priorities while keeping the team focused on successful project delivery.
KEY RESPONSIBILITIES:
- Own the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.
- Partner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.
- Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
- Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.
- Establish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.
- Drive design optimization for timing, power, area, and design-cycle efficiency.
- Develop and enhance scripts and automated design flows to improve physical design execution.
- Provide technical leadership and mentoring to engineers throughout design closure.
- Collaborate across geographically distributed engineering teams to deliver projects against technical requirements.
PREFERRED EXPERIENCE:
- Strong experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.
- Experience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.
- Experience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.
- Experience with physical design and signoff tools such as Synopsys ICC2, ICC, Fusion Compiler, PrimeTime and StarRC; Mentor Graphics Calibre; Apache RedHawk; and Cadence Innovus and Genus.
- Experience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.
- Experience with advanced process technologies, including N2P or below.
- Proficiency with Python and TCL for design-flow development and automation.
- Experience leading engineers through design closure and providing technical mentorship.
- Familiarity with RTL design, logic-level optimization, and computer organization/architecture.
- Experience applying or developing AI techniques for performance, power, and area optimization is desirable.
ACADEMIC CREDENTIALS:
- Bachelors or Masters in Electronics/Electrical Engineering preferred.
LOCATIONS:
- Vancouver, BC or Markham, ON
#LI-LC3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.