ASIC Digital Design, Sr Engineer Yerevan, Armenia

Synopsys · Yerevan

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You Are

You are an ASIC digital designer who has taken RTL modules from specification through implementation and into production silicon. You write timing-aware Verilog, and you use synthesis, timing, and power results to improve your designs. You work closely with architecture, verification, and physical design, and you raise tradeoffs early so performance, area, and power stay aligned with the schedule. When specifications change, you analyze the impact and propose a practical path forward. At Synopsys, you will design modules in the UCIe Controller IP used in high-performance computing applications.

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