R&D Engineering, Staff Engineer

Synopsys · Sunnyvale

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We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years understanding that clock networks are not just routing problems, they are the heartbeat of every chip, and when they fail, everything downstream pays the price. You know the difference between a clock tree that closes timing and one that creates more problems than it solves, and you have debugged enough customer designs to spot the warning signs three steps earlier than most engineers.

You are comfortable moving between algorithm development in C++ and customer debug sessions where you need to explain why their skew target is fighting their power budget. You do not just run tools, you understand what the tools are doing under the hood, and when the methodology needs to change, you are the one who figures out what comes next.

You like hard problems. Balancing skew, insertion delay, power, and timing across advanced nodes is not a checkbox exercise, it is a series of tradeoffs that require both technical depth and judgment. You ask the right questions, you push back when something does not make sense, and you do not settle for 'good enough' when the design can be better.

At Synopsys, you will work on Fusion Compiler, the tool that powers physical design for the most advanced chips in the world. The problems are real, the customers are demanding, and what you build will matter.

What You'll Be Doing

• Develop and enhance clock tree synthesis and clock optimization algorithms in Fusion Compiler, focusing on skew balancing, useful skew, buffering strategies, and insertion delay optimization
• Debug timing and clocking issues in customer designs across advanced process nodes (16nm to 5nm), identify root causes, and translate findings into product improvements
• Design and prototype new CTS and post-CTS optimization flows that integrate into customer methodologies and improve quality of results, runtime, and convergence predictability
• Collaborate directly with R&D engineers, Customer Application Engineers, and Account Consultants to understand real-world design challenges and align product direction with customer needs
• Implement and test new features in C++, Python, and Tcl, ensuring correctness, performance, and maintainability across large, complex codebases
• Analyze clock architecture tradeoffs including skew, latency, OCV-aware optimization, and uncertainty to drive better design outcomes across market verticals
• Contribute to continuous improvement of clock quality of results, addressing power, timing closure, and robustness across evolving process technologies

The Impact You Will Have

• Improve clock tree synthesis capabilities in Fusion Compiler, directly affecting timing closure success for customers designing AI accelerators, mobile processors, and automotive chips
• Enable better skew, insertion delay, and power outcomes for next-generation designs, reducing customer iteration cycles and improving time to tapeout
• Drive clock network quality and scalability improvements that make advanced node designs more predictable and less prone to late-stage surprises
• Help customers achieve signoff convergence faster by improving the robustness and accuracy of clock optimization flows
• Influence the direction of physical design technology by solving problems that affect how the semiconductor industry implements clock networks at scale
• Contribute to solutions that power high-performance, low-power silicon across industries, from data centers to edge devices
• Strengthen Synopsys' position as the leader in EDA by delivering clock implementation technology that sets the standard for the industry

What You'll Need

• Master's degree in Computer Science, Computer Engineering, Electronics Engineering, Mathematics, or related field with 2+ years of professional experience, or Ph.D. in a related field
• Strong proficiency in C++ for performance-critical algorithm development and systems software
• Experience with clock tree synthesis, static timing analysis, timing closure, or physical synthesis flows in an EDA or semiconductor design context
• Solid understanding of clock architecture concepts including skew, latency, insertion delay, transition, uncertainty, and OCV-aware optimization
• Familiarity with VLSI processes and physical design methodology, including timing, area, power, congestion, and signal integrity tradeoffs
• Working knowledge of Python and Tcl for scripting, automation, and tool integration
• Experience with advanced technology nodes (16nm to 5nm) is a plus, understanding the unique challenges of finFET and gate-all-around processes strengthens your ability to solve real customer problems

Who You Are

• You can take a customer design that is failing timing closure, trace the issue back to a clock tree decision made earlier in the flow, and explain the fix in terms the customer actually understands
• You are comfortable working in ambiguity, whether that means prototyping a new algorithm without a perfect spec or debugging a complex interaction between clock optimization and placement
• You push back when a proposed feature does not align with how customers actually work, and you do it in a way that moves the conversation forward instead of shutting it down
• You keep multiple threads moving at once, balancing algorithm development, customer debug, and collaboration with cross-functional teams without losing track of what matters most
• You care about the details, not because you are a perfectionist, but because you know that a small mistake in a clock tree can cascade into a multi-week delay for a customer
• You are resourceful, when you hit a wall, you find another way through, whether that means diving into unfamiliar code, reaching out to a colleague, or rethinking the problem from scratch

The Team You'll Be Part Of

You will join the CTS and clock optimization R&D team within the Design Implementation group. This team is focused on advancing clock implementation technology in Fusion Compiler, working on problems that directly affect timing closure, power, and design predictability for the most advanced chips in the industry. You will collaborate closely with fellow R&D engineers, Customer Application Engineers, and Account Consultants, balancing product development with real-world customer engagement. The team values technical depth, practical problem solving, and a willingness to tackle hard challenges that move the industry forward.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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