Technical Architect
HCLTech · United States
Job Summary
We are seeking a senior Full-Chip EMIR / Power Integrity Engineer to lead the reliability analysis and sign-off closure for our next-generation, large-scale digital ASICs and SoCs. In this high-impact role, you will architect the full-chip Power Distribution Network (PDN), manage top-level bump/pad planning, and execute static and dynamic IR drop and electromigration (EM) analyses. You will aggregate block-level power models, analyze peak-current switching scenarios, and drive chip-package-board co-optimization to guarantee complete power delivery integrity and silicon reliability before tape-out.
Key Responsibilities
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Skills:
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Skill Requirements
Synopsys-Apache Redhawk (RHSC) and or Cadence - Voltus IR/DVD tool