Senior Designer

Job Summary

Band    Designation    Job Description
E1    DFT Enginner    B.Tech / M.Tech with 2 to 4 years of experience exclusively in DFT.
        Strong Digital and STA, VLSI flow, Verilog, Scripting concepts.
        "Block or Sub-system level:
Hands-on experience to do scan insertion, ATPG DRC, Coverage Analysis, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing."
        "Block or Sub-system level:
Hands-on Experience to do MBIST Verification, DFX feature verification, Pattern generation."
        Working knowledge of JTAG, iJTAG, ICL, PDL etc.
        Good at Communication, self driven VLSI professional

Key Responsibilities

Band    Designation    Job Description
E1    DFT Enginner    B.Tech / M.Tech with 2 to 4 years of experience exclusively in DFT.
        Strong Digital and STA, VLSI flow, Verilog, Scripting concepts.
        "Block or Sub-system level:
Hands-on experience to do scan insertion, ATPG DRC, Coverage Analysis, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing."
        "Block or Sub-system level:
Hands-on Experience to do MBIST Verification, DFX feature verification, Pattern generation."
        Working knowledge of JTAG, iJTAG, ICL, PDL etc.
        Good at Communication, self driven VLSI professional

Skill Requirements

Other Requirements