Layout Design, Sr Staff Engineer
Synopsys · Noida
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the trenches of physical design, where a misplaced power ring or a routing bottleneck can turn a promising memory macro into a timing nightmare. Layout is not just drawing rectangles to you, it is solving a puzzle where every micron counts and every decision ripples through verification, performance, and yield. You know that the difference between a memory compiler that ships and one that gets stuck in debug is usually a floor plan decision made two weeks earlier, and you are the kind of engineer who sees that coming.
You are comfortable moving between Calibre or ICV verification runs, XARA power analysis, and sitting with circuit designers to understand why a bitcell is behaving the way it is. When a DRC violation shows up at tape-out minus two days, you do not panic, you methodically trace it back, fix it, and document it so it does not happen again. You have strong opinions about power grid design and you can back them up with IR drop numbers.
At Synopsys, you will work on memory IP that goes into chips powering everything from AI accelerators to automotive systems. The layouts you own will be used by customers worldwide, and the quality bar is exactly as high as you would expect.
What You'll Be Doing
- Design and own full custom layouts for embedded memory blocks, including SRAM, register files, and ROM compilers across advanced process nodes
- Develop floor plans, place memory cells and periphery blocks, route power grids and signal interconnects to meet area, performance, and power targets
- Run IR drop and electromigration analysis using tools like XARA, back-annotate layout parasitics, and iterate with circuit teams to close timing and power
- Execute physical verification using DRC and LVS tools such as ICV or Calibre, debug violations, and drive layouts to clean signoff
- Collaborate with memory compiler architects and circuit designers to translate specifications into manufacturable, verified layout deliverables
- Script layout automation flows using TCL, Perl, or C-shell to improve productivity and ensure consistency across memory variants
- Support formal release cycles, including documentation, design rule checks, and handoff to product engineering and customers
The Impact You Will Have
- Enable Synopsys memory IP to meet aggressive PPA targets that directly affect customer chip performance and power efficiency
- Reduce layout development cycle time through automation and reusable design practices, accelerating time to market for new memory products
- Ensure memory macros pass physical verification and reliability checks on the first pass, minimizing costly respins and customer escalations
- Contribute to the quality and competitiveness of Synopsys memory compiler offerings used in high-volume production across automotive, mobile, and AI markets
- Influence layout methodology and best practices that shape how the team approaches next-generation process nodes
- Mentor junior layout engineers and share knowledge that raises the overall capability of the physical design team
- Support customer engagements by delivering robust, well-documented layouts that integrate cleanly into complex SoC designs
What You'll Need
- Diploma in Electronics Engineering with 8+ years of layout design experience, or BE/BTech with 6+ years, or MS with 4+ years in a directly relevant role
- Deep hands-on experience with full custom layout design for embedded memories including floor planning, placement, power grid design, and signal routing
- Proficiency with layout tools such as Cadence Virtuoso or Custom Compiler, and physical verification tools like Mentor Calibre or Synopsys ICV
- Strong understanding of IR drop and electromigration analysis, including use of tools like XARA or RedHawk, and ability to close power integrity issues
- Solid knowledge of physical design methodologies across all phases: floor planning, place and route, DRC/LVS verification, and signoff
- Scripting capability in TCL, Perl, or C-shell to automate layout tasks and improve design flow efficiency
- Experience with memory compiler development, block placement, and parasitic-aware layout optimization is a strong plus
Who You Are
- You can look at a layout and immediately spot the power grid weakness or the routing congestion that will cause problems three steps downstream
- When a circuit designer asks for a layout change that breaks your carefully optimized floor plan, you do not just say no, you explain the tradeoff and propose an alternative that works for both of you
- You keep your manager informed without being asked, you know when a schedule is slipping and you surface it early with a plan, not just a problem
- You are the person the team comes to when a tough DRC violation will not go away, because you have the patience and the methodology to track it down
- You adapt quickly when process rules change or a new node brings unexpected challenges, and you help the rest of the team do the same
- You take initiative to learn new tools and techniques, and you share what you learn so the whole team gets better
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process