Design Verification Engineer
Apple · Austin
- Design Verification Engineer
- Austin Metro Area, Texas, United States
- Hardware
- Submit Resume
- Summary
- Posted:
- Oct 29, 2026
- Role Number:
- 200691993-0240
- At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.
- This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
- Description
- In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
- Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
- Responsibilities
- Study design specification and create test plan
- Develop infrastructure in SystemVerilog/UVM to stress the design
- Develop and fix failures from regressions, close bugs
- Use LLMs to do verification efficiently
- Minimum Qualifications
- BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent.
- Preferred Qualifications
- MS degree in a technical subject area and relevant industry experience strongly preferred
- Strong knowledge of OOP, SystemVerilog and UVM
- Strong knowledge in developing scalable and portable testbenches
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, and gate-level simulations
- Working experience using LLMs for efficiency and quality
- Experience with power-aware (UPF) or similar verification methodology
- Knowledge of one of the scripting languages such as Python, Perl, TCL
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
- Knowledge of formal verification methodology is a plus but not required
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