Senior Custom SOC IP Verification Engineer
Nvidia · Shanghai
NVIDIA NVLink™ Fusion delivers industry-leading AI scale-up and scale-out performance with NVIDIA technology plus semi-custom ASICs or CPUs . NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation NVLink Fusion semi-custom silicon. We are looking for special individuals with passion and desire to deliver innovative products. If you are a motivated individual that understands how complex SOC and IPs are built, and understand various development cycles, this is your place to be.
What you'll be doing:
Responsible for ASIC design verification for various IPs at IP and SOC levels
Responsible for reference model development and integration
Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans
Contribute to the innovative verification methodology development, functional and code coverage closure.
Work on the complex TB creation, direct/random tests and drive the function and coverage to closure.
Contribute to the development of silicon and platform verification strategy and methodology
Triage the fail on SOC level with SOCV/EMU/SW team
Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
What we need to see:
Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
Track record of first-pass success in ASIC Development
B.S. or M.S. degree in Computer Engineering or Electrical Engineering
Experience working across multiple projects and adjusting priorities in partnership with stakeholders
5+ years of experience owning processing ASIC, IP or SoC design verification
Experience managing and delivering complex mixed language UVM and C++ testbenches
Ability to interpret functional specs and creating comprehensive test plans
Ability to write directed and constraint random test to achieve coverage-driven verification closure
Strong programming skills in C++/SystemC. Familiar with the GDB debugging.
Experience developing tools and infrastructure using Perl or Python
Ways to stand out from the crowd:
Hands-on background with AMBA protocols such as AXI, ACE, CHI, etc.
Hands-on experience with complex subsystems in new technologies like ARM CPU complex, LPDDR, HBM, GPU’s, UCIE, PCIE or Network on chip and with performance verification